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EMIF02-USB01F2
2-line IPADTM, EMI filter including ESD protection
Features

2-line low-pass filter + ESD protection High efficiency in EMI filtering Lead-free package Very low PCB space occupation: < 2.5 mm2 Very thin package: 0.65 mm High efficiency in ESD suppression (IEC61000-4-2 level 4) High reliability offered by monolithic integration High reduction of parasitic elements through integration and wafer level packaging Figure 1. Pin configuration (bump side view)
3
Pup
Flip Chip (8 bumps)
2
1
Vbus
Complies with the following standards
DZ
A B
IEC 61000-4-2 level 4 - 15 kV (air discharge) - 8 kV (contact discharge)
D+ in GND Din
D+ out
C D
Dout
E
Application
ESD protection and EMI filtering for:
Figure 2.
Schematic
Pup
USB port
Vbus 1.3K 33 DZ D+ out
Description
The EMIF02-USB01F2 is a highly integrated array designed to suppress EMI / RFI noise for USB port filtering. The EMIF02-USB01F2 Flip Chip packaging means the package size is equal to the die size. Additionally, this filter includes ESD protection circuitry which prevents damage to the protected device when subjected to ESD surges up to 15 kV.
D+ in
GND
33 D- out D- in
TM: IPAD is a trademark of STMicroelectronics.
April 2008
Rev 3
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Electrical characteristics
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EMIF02-USB01F2
1
Electrical characteristics
Table 1.
Symbol Tj Top Tstg
Absolute ratings (Tamb = 25 C)
Parameter junction temperature Operating temperature range Storage temperature range Value 125 -40 to +85 -55 to 150 Unit C C C
Table 2.
Symbol VBR IRM VRM VCL Rd IPP RI/O Cline Symbol VBR IRM Cline R1, R2 R3
Electrical characteristics (Tamb = 25 C)
Parameters Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic impedance Peak pulse current Series resistance between input and output Input capacitance per line Test conditions IR = 1 mA VRM = 3 V @0V Tolerance 5 % Tolerance 5 % 40 33 1.30 Min 6 0.5 45 Typ Max Unit V A pF k
slope: 1/Rd
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EMIF02-USB01F2
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Figure 3.
0.00 dB -5.00 -10.00
S21 (dB) attenuation measurement Figure 4.
0.00 dB -10.00 -20.00 -30.00
Analog crosstalk measurements
EMIF02-USB01: filtering response of lines C1/C3 and E1/E3
-15.00
-40.00
-20.00
-50.00
-25.00 -30.00 -35.00 -40.00 -45.00 -50.00 1.0M E1_E3 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G C1_C3 3.0G
-60.00 -70.00 -80.00 -90.00 -100.0 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G
Frequency/Hz
f/Hz
Figure 5.
ESD response to IEC61000-4-2 (+15 kV air discharge) on one input V(in) and on one output (Vout)
Figure 6.
ESD response to IEC61000-4-2 (-15 kV air discharge) on one input V(in) and on one output (Vout)
Vin : 10V/d
Vin : 5V/d
Vout : 10V/d
100ns/d
Vout : 5V/d
100ns/d
Figure 7.
Capacitance versus reverse applied voltage (typical)
C(pF)
40 35 30 25 20 15
VR(V)
10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
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Application information
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EMIF02-USB01F2
2
Application information
Figure 8.
3.8nH C1 Csub rsub_1k3 rsub_1k3 Csub
Aplac model (resistors, diodes and bumps and ground connections)
R_1k3 A3
0.15nH D02_usb A1, A3, B2, C1, C3, E1, E3
Cbump Rsubump I/O bulk
D2
Lbump 100m D2 bulk Rbump
bulk 0.15nH cap_33R R_33R Csub rsub_33R Csub rsub_33R 0.23nH C3 cap_33R
Lgnd_D Rsub_D D02_usb D02_Nw
Lhole caphole Rhole
D2
bulk
bulk 0.3nH E1 cap_33R Csub rsub_33R Csub rsub_33R R_33R 0.7nH E3 cap_33R
bulk
Figure 9.
Aplac model parameters
R_33R 33.9 cap_33R 1.2pF R_1k3 1.3k Cz29pF Rsub_D 100 Csub0.3pF Rsub_33R 15 Rsub_1k3 50 lhole10pH Rhole400m Caphole0.4pF Lgnd_D 150pH Lbump50pH Rbump50m Cbump1.5pF Rsubump150 Model D02_Nw BV=100 IBV=1m CJO=6.8p M=0.3333 RS=2 VJ=0.6 TT=100n Model D02_usb BV=16 IBV=1m CJO=Cz M=0.3333 RS=2 VJ=0.6 TT=100n
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EMIF02-USB01F2
www..com Ordering information scheme
3
Ordering information scheme
Figure 10. Ordering information scheme
EMIF
EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package F = Flip Chip X = 2: Lead-free, pitch = 500 m, bump = 315 m
yy
-
xxx zz
Fx
4
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 11. Package dimensions
700 50 315 50 650m 65
49
5
m
50
285 m
285m
1.27mm 50m
1.97mm 50m
5 49 m 50
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Ordering information
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EMIF02-USB01F2
Figure 12. Footprint
Copper pad Diameter: 250 m recommended, 300 m max
Figure 13. Marking
Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week)
E
Solder stencil opening: 330 m
Solder mask opening recommendation: 340 m min for 315 m copper pad diameter
xxz y ww
Figure 14. Flip Chip tape and reel specification
Dot identifying Pin A1 location 4 0.1 O 1.5 0.1
1.75 0.1 3.5 0.1
2.07
0.73 0.05
All dimensions in mm
8 0.3
STE
STE
STE
xxz yww
User direction of unreeling
xxz yww
xxz yww
4 0.1
1.37
5
Ordering information
Table 3. Ordering information
Marking FF Package Flip Chip Weight 3.35 mg Base qty 5000 Delivery mode Tape and reel 7"
Order code EMIF02-USB01F2
Note:
More information is available in the application notes: AN1235:"Flip Chip: Package description and recommendations for use" AN1751: "EMI filters: Recommendations and measurements"
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EMIF02-USB01F2
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Revision history
6
Revision history
Table 4.
Date 26-Oct-2004 16-Apr-2007 29-Apr-2008
Document revision history
Revision 1 2 3 Initial release. Updated ECOPACK statement. Updated Figure 10, Figure 11 and Figure 14. Reformatted to current standards. Typographical errors corrected. Changes
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EMIF02-USB01F2
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